The Equation Series
Menu

Industry study 12 of 24 · Manufacturing Research Companion: Companies, Strategic Moves, and Technical Studies

Semiconductor Fabrication as Manufacturing

~7,000 words · 1 technical exhibit

A leading-edge chip fab is the most capital-intensive factory ever built. A single site costs $20bn or more. Its cleanrooms hold hundreds of tools priced from a few million dollars to more than $350m for a High-NA EUV scanner (reported, verify). It processes 300 mm silicon wafers through roughly 1,000 or more steps over two to three months (common ranges, verify), and depreciation, not labour, sets most of the cost of a wafer. The US built ~37% of the world's chips in 1990 and ~12% by 2020 (an often-cited SIA/BCG estimate, verify). The 2022 CHIPS Act set out to reverse that with $39bn of manufacturing incentives and $11bn for R&D (statutory, from memory, verify). By late 2026 the result was mixed:

What the study covers

  1. 1Overview: the factory where yield is the product
  2. 2How a chip is made
  3. 3Yield, defect density and the ramp
  4. 4Tools and the toolmakers
  5. 5Foundry vs IDM
  6. 6Memory, mature nodes and power chips
  7. 7US fabs and CHIPS after the renegotiations
  8. 8Section 232 semiconductors and other trade measures
  9. 9Europe and Asia
  10. 10How to read fab claims
  11. 11Key numbers
  12. 12Landmark companies and cases
  13. 13Pitfalls
  14. 14How an expert thinks about it
  15. 15Glossary

Technical exhibits

Worked examples, checklists and case studies included with this study.

Wafer Cost Die Yield and Defect Density Worked Example

A stylized US foundry: dies per 300 mm wafer and Murphy yield for 100, 300 and 800 mm² dies; cost per good die as D0 falls from 0.5 to 0.07; the value of cutting D0 from 0.3 to 0.1 (~70% lower cost for an 800 mm² die); chiplets; a two-year yield ramp (~27% of output forgone); location premium vs yield; depreciation per wafer (computed in Python)

Companies in this study