Every AI product, from a chatbot answer to a self-driving car's next turn, ends as arithmetic on a chip. Modern AI is mostly one operation, multiplying large matrices of numbers, repeated trillions of times a second, and the companies that make chips which do this quickly, cheaply and at scale took the first and largest profits of the generative-AI boom. Nvidia reported data-centre revenue of ~$193.7 billion in the fiscal year to January 2026, up from ~$15 billion three years earlier, at gross margins in the low-to-mid 70s per cent (company filings). Behind that headline sits a supply chain with chokepoints at every stage: one company (ASML) makes the extreme-ultraviolet lithography machines that print leading-edge chips; one foundry (TSMC) manufactures nearly all advanced AI accelerators and owns most of the advanced-packaging capacity (CoWoS) that joins them to memory; three companies (SK Hynix, Samsung and Micron) make the high-bandwidth memory (HBM) every accelerator needs; and most of it happens in Taiwan and South Korea. An AI chip business is therefore an answer to five questions: how much useful work does the chip deliver per dollar and per watt, what software ecosystem makes that work easy to use, who controls the scarce inputs (wafers, packaging, memory, lithography), who are the few customers buying most of the output, and what happens when export controls, a product transition or a slowdown in data-centre spending arrives? This section explains how accelerators work and why memory and packaging, not only transistors, are the bottlenecks; maps the stack from lithography to rack-scale systems; covers GPUs, Nvidia's CUDA moat, challengers, custom ASICs (Google's TPU, Amazon's Trainium, the Broadcom-designed chips for Meta and OpenAI), HBM, foundry, packaging, lithography and networking; sets out margins and key numbers; and closes with cases, pitfalls and how practitioners think. A worked example compares the total cost of ownership of a merchant-GPU fleet with a custom-ASIC fleet, and a checklist sets out diligence questions by layer.
What the study covers
- 1Overview: why chips became the first bottleneck
- 2The chip stack: who does what
- 3Mechanics
- 4Margins and economics by layer
- 5Export controls, industrial policy and Taiwan
- 6Key numbers
- 7Landmark companies and cases
- 8Pitfalls
- 9How an expert thinks about it
- 10Glossary
Technical exhibits
Worked examples, checklists and case studies included with this study.
GPU vs Custom Asic Tco Worked Example
A stylized inference fleet built with merchant GPUs versus a custom ASIC: annual cost per unit of delivered work, break-even fleet size for the ASIC's design cost, and the sensitivities (GPU price cuts, ASIC performance and utilisation, design cost, power price, chip life) that decide the answer (computed in Python)
AI Semiconductor Diligence Checklist
Questions to ask of any AI chip, memory, foundry, packaging, equipment or systems business, by layer, with red flags